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this product conforms to specifications per the terms of the ramtron standard warranty. the product has completed ramtrons internal qualification testing and has reached production status. cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 84506 rev. ** revised february 2 5 , 2013 fm 25w256 256kb wide voltage spi f - ram features 256k bit ferroelectric nonvolatile ram organized as 32,768 x 8 bits high endurance 100 trillion (10 14 ) read/writes 38 year data retention ( @ +75oc) nodelay? writes advanced high - reliability ferroelectric process very fast serial peripheral interface - spi up to 20 mhz frequency direct hardware replacement for eeprom spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) write protection scheme hardware protection software protection low power operation wide voltage operation 2.7 v C 5.5v 15 a (typ.) standby current industry standard configurations industrial temperature - 40 c to +85 c 8 - pin green/rohs soic ( - g ) description the fm 25w256 is a 256 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provides reliabl e data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm25w256 performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after it has been successfully transferred to the device. the next bus cycle may commence immediately without the need for data polling . in addition, the product offers substantial write endurance compared with other nonvolatile memories. the fm25w256 is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom . these capabilities make the fm 25w256 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eepro m can cause data loss. the fm 25w256 provides substantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm 25w256 uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. device specificat ions are guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage ( 2.7 to 5.5v) vss ground ordering information fm 25w256 - g green green/rohs 8 cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 2 of 14 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active low input activates the device. when high, the device enters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs m ust occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the status register only. a complete explanation of write protection is provided on pages 6 and 7. si input serial input: all data is input to the device on this pin. the pin i s sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * si may be connected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply: 2.7 v to 5.5v vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 4 k x 64 fram array 15 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 3 of 1 4 overview the fm 25w256 is a serial f - ram memory. the memory array is logically organized as 32,768 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25w256 and a serial eeprom with the same pinout is the f - ram s superior write performance and power consumption. memory architecture when accessing the fm 25w256 , the user addresses 32k locations of 8 data bits each. these data bits are shifted serially. the addresse s are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and a two - byte address. the upper bit of the address range is a dont care value. the complete address of 15 - bits specifies each byte address uniquely. most functions of the fm 25w256 either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. tha t is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write o peration will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm 25w256 due to its fast write cycle and high endurance as compared to eeprom. in addition there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note that the fm 25w256 contains no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended tha t the part is not powered down with chip enable active. serial peripheral interface C spi bus the fm 25w256 employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high - speed serial bus provides high perform ance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25w256 operates i n spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25w256 devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. no te that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25w256 device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to redu ce hardware resources on the controller, it is possible to connect the two data pins together and tie off the hold pin. figure 3 shows a configuration that uses only three pins. protocol overview the spi interface is a synchronous serial interface using c lock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm 25w256 will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm 25w256 supports only modes 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm 25w256 on the rising edge of sck and data is expected on the first rising edge afte r /cs goes active. if the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: the /cs must go in active after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 4 of 14 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 microcontroller fm 25w256 so si sck cs hold p 1 . 0 p 1 . 1 p 1 . 2 spi microcontroller fm 25w256 so si sck cs hold fm 25w256 so si sck cs hold sck mosi miso ss 1 ss 2 hold1 hold2 mosi : master out slave in miso : master in slave out ss : slave select 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 5 of 1 4 power up to first access the fm 25w256 is not accessible for a period of time (t pu ) after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first /cs low. data transfer all data transfers to and from the fm 25w256 occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of sck. outputs are driven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm 25w256 . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register. the third group includes commands for memory transactio ns followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b wren C set write enable latch the fm 25w256 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the us er to issue subsequent op - codes for write operations. these include writing the status register and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates th e state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit. completing any write operation will automatically clear the write - enable latch and prevent furth er writes without another wren command. figure 5 illustrates the wren command bus configuration. wrdi C write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 cs sck si so
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 6 of 1 4 figure 6. wrdi bus configuration rdsr C read status register the rdsr command allows the bus master to verify the contents of the status reg ister. reading status provides information about the current state of the write protection features. follo wing the rdsr op - code, the fm 25w256 will return one byte with the contents of the status reg ister. the status reg ister is described in detail in a later section. wrsr C write status register the wrsr command allows the user to select certain write protec tion features by writing a byte to the status reg ister. prior to issuing a wrsr command, the /wp pin must be high or inactive. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a wr ite operation and therefore clears the write enable latch. figure 7. rdsr bus configuration figure 8. wrsr bus configuration status register & write protection the write protection features of the fm 25w256 are multi - tiered. taking the /wp pin to a logic low state is the hardware write protect function. all write operations are blocked when /wp is low. to write the memory with /wp high, a wren op - code must first be issued. assuming that writes are enabled using wren and by /wp, writes to memor y are controlled by the status r egister. as described above, writes to the status register are performed using the wrsr command and subject to the /wp pin. t he status reg ister is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 and cannot be modified. note that bit 0 (ready in eeproms) is unnecessary as the f - ram writes in real - time and is never busy. the bp1 and bp0 control software write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status reg ister has no e ffect on its state. this bit is internally set by the wren command and cleared cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 7 of 1 4 by terminating a write cycle (/cs high) or by using the wrdi command. bp1 and bp0 are memory block write protection bits. they specify portions of memory that ar e write protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 6000h to 7fffh (upper ?) 1 0 4000h to 7fffh (upper ?) 1 1 0000h to 7fffh (all) the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware / wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register. thus the status reg ister is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can pr event software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware pr events altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protecti on wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25w256 can perform sequential writes at bus speed. no page register is needed an d any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code is followed by a two - byte address value. the upper bit of the address is a dont care. in total, 15 - bits specify the address of the first data byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7fffh is reached, the counter will roll over to 0000h. data is written msb first. a write operation is shown in figure 9. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately af ter it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation. asserting /wp active in the middle of a write operation will have no e ffect until the next falling edge of /cs. read operation after the falling edge of /cs, the bus master can issue a read op - code. following this instruction is a two - byte address value. the upper bit of the address is a dont care. in total, 15 - bits specify the address of the first byte of the read operation. aft er the op - code and address are complete, the si line is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 7fffh is reach ed, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read op - code operation. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck and /cs pins can toggle during a hold state.
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 8 of 14 figure 9. memory write (wren must precede write) figure 10. memory read endurance the fm 25w256 device is capable of operating at least 10 14 read or write cycles. a f - ram memory op erates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a14 - a3 and column ad dresses by a2 - a0. see block diagram (pg 2) which shows the array as 4k rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an enduranc e calculation. the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream. this causes each byte to experience one endurance cycle through the loop. f - ram re ad and write endurance is virtually unlimited even at 20mhz clock rate . table 5. time to reach endurance limit for repeating 64 - byte loop sck freq (mhz) endurance cycles /sec. endurance cycles/year years to reach 10 14 cycles 20 37,31 0 1.18 x 10 12 85.1 10 18,660 5.88 x 10 1 1 170.2 5 9,33 0 2.94 x 10 1 1 340.3 cs sck si so 0 1 2 3 4 5 6 7 0 0 hi-z 1 msb lsb 0 1 2 3 4 6 7 x 0 op-code 16-bit address 0 0 1 11 12 13 14 0 1 2 3 4 5 6 7 7 data in 0 1 2 3 4 5 6 msb lsb 7 0 0 0 0 cs sck si so 0 1 2 3 4 5 6 7 0 0 hi-z 1 msb lsb 0 1 2 3 4 6 7 x 0 op-code 16-bit address 0 1 11 12 13 14 0 1 2 3 4 5 6 7 7 data out 0 1 2 3 4 5 6 msb lsb 7 0 1 0 0 0
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 9 of 1 4 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any pin with respect to v ss - 1.0v to +7.0v and v in < v dd +1.0v t stg storage temperature - 55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 26 0 c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 250v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil i ty. dc operating conditions ( t a = - 40 c to + 85 c, v dd = 2.7 v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.7 3.3 5.5 v i dd power supply current @ sck = 1.0 mhz @ sck = 20 . 0 mhz - - 0. 2 5 2 .0 ma ma 1 i sb standby current 15 3 0 a 2 i li input leakage current - 1 a 3 i lo output leakage current - 1 a 3 v ih input high voltage 0.7 v dd v dd + 0.5 v v il input low voltage - 0.3 0.3 v dd v v oh output high voltage @ i oh = - 2 ma v dd C 0.8 - v v ol output low voltage @ i ol = 2 ma - 0.4 v notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss v in v dd and v ss v out v dd .
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 10 of 1 4 ac parameters ( t a = - 40 c to + 85 c , v dd = 2.7 v to 5.5v , c l = 30pf) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 2 2 ns 1 t cl clock low time 2 2 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 2 0 ns t oh output hold time 0 ns t d deselect time 6 0 ns t r data in rise time 50 ns 2, 3 t f data in fall time 50 ns 2, 3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 25 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. this parameter is characterized but not 100% tested. 3. rise and fall times measured between 10% and 90% of waveform. capacitance ( t a = 25 c, f=1.0 mhz, v dd = 5.0 v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test condi tions input pulse levels 10% and 90% of v dd input rise and fall times 5 ns input and output timing levels 0.5 v dd output load capacitance 30 pf data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 11 of 1 4 serial data bus timing /hold timing power cycle timing power cycle timing ( t a = - 40 c to + 85 c, v dd = 2.7 v to 5.5v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 - ms t pd last access complete to v dd (min) 0 - s t v r v dd rise time 3 0 - s/v 1 t vf v dd fall time 3 0 - s/v 1 notes 1. sl ope measured at any point on v dd waveform . s c d q 1 / t c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f s c q hold t hs t hh t hz t lz t hs t hh v d d m i n . v d d c s t v r t p d t p u t v f
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 12 of 1 4 mechanical drawing 8 - pin soic (jedec ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxx xxx = part number, p= package type (g=soic) lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 25w256 , green soic package, year 2010 , work week 39 fm 25w256 - g a 00002g1 ric10 39 xxxx xxx - p ll llll l ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 0 . 40 1 . 27 0 . 19 0 . 25 0 - 8 recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 13 of 1 4 revision history revision date summary 1.0 11/19 /2010 initial release 1.1 12/8/2010 fixed endurance section on pg 8. 1.2 1/11 /2011 add esd ratings. 1.3 2/15/2011 changed t pu and t vf timing parameters. 2 .0 1/6/2012 changed to pre - production status. changed t vf spec. 2.1 5/15/2012 improved t pu timing parameter. 3.0 10/9/2012 moved to production status. document history document title: fm2 5 w256 256 k b serial wide vol ta ge spi f - ram document number: 001 - 8 4 506 revision ecn orig. of change submission date description of change ** 3912930 gvch 02/25/2013 new spec
fm25w256 - 256kb spi f - ram document number: 001 - 84506 rev. ** page 14 of 1 4 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go /a utomotive clocks & buffers cy press.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ramtron is a registered trademark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor corporation, 2011 - 2013 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medi cal, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life - support systems where a malfu nction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress a gainst all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldwide patent protection (united states and foreign), united states copyright laws and internation al treaty provisions. cypress hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom s oftware and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or representation of this source cod e except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merch antability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does no t assume any liability arising out of the application or use of any product or circuit desc ribed herein. cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement .

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